Cadence Design, TSMC expand partnership on IP and photonics design

Cadence Design (CDNS) and TSMC (TSM) have extended their longstanding collaboration by announcing a broad range of innovative technology advancements to accelerate design, including developments ranging from 3D-IC and advanced process nodes to design IP and photonics. This collaboration significantly advances system and semiconductor design for AI, automotive, aerospace, hyperscale and mobile applications and has resulted in the following recent technology achievements: Cadence collaborates with TSMC to infuse the Integrity(TM) 3D-IC platform with new features and functionality: The Cadence Integrity 3D-IC platform, the industry’s comprehensive solution certified for all the latest TSMC 3DFabric(TM) offerings, now supports a hierarchical 3Dblox specification developed to integrate multiple chiplets into hierarchies for reuse and modular design. It also includes new features developed to ease chiplet assembly and design, and an automated alignment markers insertion flow to accelerate the design and assembly of stacked chiplets on different interposers and packages. Cadence’s digital solutions are certified for TSMC N2 design flow, including Innovus(TM) Implementation System, Quantus(TM) Extraction Solution, Quantus Field Solver, Tempus(TM) Timing Signoff and ECO Solution, Pegasus(TM) Verification System, Liberate(TM) characterization, and the Voltus(TM) IC Power Integrity Solution. The Genus(TM) Synthesis Solution is also enabled for N2 technology. Cadence and TSMC are collaborating on AI-driven Cadence solutions to enable an AI-assisted design flow for productivity and optimization of PPA results. The Cadence Custom/Analog Design Flow is fully certified for TSMC’s latest N2 Process Design Kit (PDK): Cadence custom tools optimized for TSMC N2 PDKs include Virtuoso(R) Schematic Editor for design capturing and the Virtuoso ADE Suite for analysis, which are both part of Virtuoso Studio, and the integrated Spectre(R) Simulator. All have been enhanced for managing corner simulations, statistical analyses, design centering, and circuit optimization, which are now common with advanced nodes. Virtuoso Studio has also been augmented to support front-to-back process migration from schematic mapping to optimized design specifications to full-layout place-and-route automation. The Virtuoso Studio and Spectre Simulation platforms, including Spectre X, Spectre XPS and the Spectre RF Option, have achieved the latest TSMC N2 certifications. Cadence and TSMC have worked closely together to release a Virtuoso Studio N16 to N6 RF migration reference flow to substantially reduce turnaround time: Purposed-based instance mapping rapidly retargets schematics, while EMX(R) Planar 3D Solver provides inductor synthesis and EM extraction for nets and components during the design phase. The Virtuoso ADE Suite provides design optimization using Spectre Simulation’s RF analysis capabilities, and Virtuoso Studio Layout tools accelerate the reuse and reimplementation of RF layouts while preserving design intent.”