Cadence Design, TSMC partner on chip design automation and IP

Cadence (CDNS) announced major advancements in chip design automation and IP, driven by its long-standing relationship with TSMC (TSM) to develop advanced design infrastructure and accelerate time to market, for AI and HPC customer applications. Cadence and TSMC have collaborated closely across the spectrum from AI-driven EDA to 3D-ICs to IP and photonics, enabling the world’s most advanced semiconductors. Cadence and TSMC have partnered on AI-driven design solutions for joint customers, enabling chip development with optimal power, performance and area (PPA) in TSMC N2. TSMC has enabled Cadence JedAI Solution, Cadence Cerebrus(R) Intelligent Chip Explorer’s AI-driven implementation technology and productivity features powered by Innovus+ AI Assistant within Cadence’s digital full flow. Additionally, TSMC has validated new AI-driven features, such as automated design rule check (DRC) violation fixing assistance, enabling faster design closure and greater efficiency in the development of AI chips using TSMC N2.”